I looked up and saw him, suddenly free from above me, floating in open air. He’d been hovering over a pale desert portrait that looks like it has no eyes left to cry with. I didn’t wonder where he came from; he just arrived. His horn doesn’t play tunes so much as make a quiet sound that demands attention. It feels exactly like the things we keep inside, trying not to let them out, until one day the walls simply can’t hold them anymore. He isn’t quite heavenly or ghostly, just something true, finally letting go.
Provenance · Integrity Record
Canonical file hashes · SHA‑512
Hashes are of the byte-identical PNGs converted from raw sensor data. Verify with sha512sum -c SHA512SUMS.
She arrived under a tower like this one, three kilometres away at Birkenau. She left as Reg. A 105, folio 9.
Auschwitz I was surrounded by a double barbed-wire fence punctuated by guard towers at regular intervals. The towers stood on the outer perimeter; the fence was electrified at high voltage. Along the fence, on the camp side, ran a gravelled strip, the "neutral zone". Camp regulations, corroborated by survivor testimony, held that guards in the towers could shoot any prisoner who entered that strip without warning. Their function was custody: to ensure that the people inside could not leave until the state had decided how they would.
On 3 September 1944, the last transport from the Westerbork transit camp to Auschwitz departed the Netherlands. It arrived at the new ramp inside Auschwitz II–Birkenau on the night of 5–6 September, after two and a half days in locked cattle wagons. Of the 1,019 Jews on the manifest, four were Franks. They appeared in sequence: Margot at 306, Otto at 307, Edith at 308, Annelies Marie at 309. By the Anne Frank House's reconstruction from the transport list and the camp number series, 648 people from the transport were registered into the camp administration after selection; 371 were sent directly to the gas chambers. The women remained at Auschwitz II–Birkenau. The men were taken to Auschwitz I, about three kilometres away; the distance and the camp's known procedures suggest they made the journey on foot. On 30 October, Margot and Anne were selected for transfer to Bergen-Belsen; the transport departed the night of 1 November and arrived on 3 November. The dates are reconstructed from survivors' letters and interviews; no transport list naming the sisters survives. Edith was left behind at Auschwitz II–Birkenau. According to the account of Rosa de Winter‑Levy, she died there in the infirmary on 6 January 1945; neither the place nor the date is confirmed by any camp record.
The Westerbork camp kept its own register. Her entry is on page 40. The pink card below is an extract citing it, preserved in her death file; the oldest documents in that file date from April 1951, so the card was most likely made in the course of postwar processing rather than at the camp. Transport: 3-9-44. Naam: FRANK. Voornamen: Annelies, M. Geboren: 12-6-29. Adres: Merwedeplein 37, Asd. It is among the last documents in the state's custody of her to record the street where she lived.
Westerborkregister · Frank, Annelies M. · transport 3-9-44 Nationaal Archief, Den Haag · 2.09.34.02, inv.nr. 539 · public domain
Bergen-Belsen maintained a prisoner registration system, so Margot and Anne would have been registered upon arrival and assigned new numbers, as was standard practice. But shortly before British forces liberated the camp on 15 April 1945, the SS burned the prisoner registration records. The numbers Anne and Margot were assigned at Bergen-Belsen are not known; neither are their Auschwitz numbers. The women of their transport were tattooed in a numbered series, but no surviving record ties either sister to a number within it. After the Westerbork transport list of 3 September 1944, no surviving document names them at all. According to eyewitness accounts and the postwar historical consensus, they died at Bergen-Belsen of typhus, probably in February 1945. The dating rests on those witness statements, on the 7 February 1945 transport list to Raguhn (which fixes the departure of witnesses who had seen them ill), on the receipt of a Red Cross parcel in late January 1945, and on the ordinary course of the disease.
For six years, the paperwork caught up slowly. The two oldest documents in her death file are forms dated 6 April 1951, in which the Commissie tot het doen van aangifte van overlijden van vermisten, the Committee for the Reporting of the Decease of Missing Persons (created under the law of 2 June 1949), wrote to the Dutch Red Cross and to the Amsterdam civil registrar to ask what was known. The Red Cross filed the Committee's request against its own record: "dossier N.R.K. 117266. Cf. concl. RK † 31 Maart 1945 te Bergen Belsen / Dld." Conclusion: died no later than 31 March 1945 at Bergen-Belsen. The Amsterdam civil registrar confirmed that no death certificate had been issued. Six years after Anne Frank's death, the municipal record said only that she had vanished and had never been declared dead.
On 7 May 1954, Johannes Kleiman, Otto Frank's colleague and one of the helpers who had hidden the Franks, wrote to the Committee as Otto's authorized representative, asking that the declarations for Margot and Anne be processed; Otto needed them to have a certificate of inheritance drawn up. The Committee acknowledged receipt on 4 June. The declaration itself was issued on 29 July 1954, in The Hague. It is the document reproduced below.
Aangifte van overlijden · No. 107658 · 's-Gravenhage, 29 Juli 1954 Commissie tot het doen van aangifte van overlijden van vermisten · Nationaal Archief 2.09.34.02, inv.nr. 539
The declaration is a typed form on light paper, numbered No. 107,658. Stamped at the top: AFSCHRIFT — copy. The printed Dutch is dense with legal procedure: Krachtens art. 2 van de Wet van 2 Juni 1949 (Stbl. No. J 227) doe ik U hierbij aangifte van het overlijden van de hieronder vermelde vermiste. By virtue of article 2 of the Law of 2 June 1949, I hereby declare the death of the missing person named below. The filled-in carbon strikes are faint: Op een en dertig Maart negentienhonderd vijf en veertig is in Bergen-Belsen in Duitsland overleden: Frank, Annelies Marie. The date is written in longhand Dutch, een en dertig Maart, the certainty the facts didn't support, spelled out word by word.
The form was sent to the Amsterdam civil registrar. Three months later, on 29 October 1954, the registrar entered the death in the municipal register in faint purple hand at the lower right: Reg. A/105. Fol. 9. Initialled and filed.
Archiefkaart · Frank, Annelies Marie Cites overlijdensakte · Burgerlijke Stand Amsterdam · Reg. A 105, Fol. 9 · d.d. 29-10-1954
The archiefkaart is Amsterdam's internal reference card for that registry entry. Printed fields in Dutch: Naam, Voornamen, Geboren op, Overleden op, Overlijdensakte opgemaakt, Bijzonderheden. The handwriting fills them in. Born 12 June 1929. Died 31 March 1945. Filed at Amsterdam on 29-10-54. Bijzonderheden (particulars): blank.
The working card that produced the date survives in the Dutch Red Cross Information Bureau's persoonsdossier on Anne Frank. It is pencil and ink, stamped 22 January 1952, a year after the statement of Lien (Lientje) Rebling-Brilleslijper, who had been imprisoned with Anne and Margot at Bergen-Belsen. In the clerk's hand at the bottom, boxed off from the rest, is the conclusion: Overleden te Bergen-Belsen niet eerder dan op 1.3.45 en uiterlijk 31.3.45. No earlier than 1 March, no later than 31 March.
Cartotheekkaartje · Frank, Annelies Marie · d.d. 22-1-1952 Nederlandse Rode Kruis, Informatiebureau · Nationaal Archief 2.19.288, inv.nr. 101677 · vervroegd openbaar gemaakt oktober 2023
The date 31 March 1945 is a bureaucratic default. It was the Committee's standard practice to date unknown deaths at the last day of the assumed month when a witness statement could establish the month. The witness statement was Brilleslijper's, given to the Dutch Red Cross on 22 January 1951. She said Anne and Margot died "around March 1945." She had put it differently elsewhere: to Otto Frank in November 1945 (the end of February or the beginning of March), and in a memoir written at his request in April 1951, where the end comes in February. The Committee picked March 31. No one then knew, and no one now knows, when Anne Frank actually died.
Her name also appears on a typed list. Lijst No. 1908. Every entry on the page is a Frank. She is fifth down: Annelies Marie, Frankfurt am Main, 12-6-1929, Bergen-Belsen, 31-3-1945. Six rows below her: Aron Moses Edward, Rotterdam, 7-8-1910, Polen, 31-3-1944. Place of death: Poland. The last day of March. Almost certainly the same administrative default, one year earlier. Near the top: Andries, Tiel, 4-3-1914, Omgeving van Auschwitz, 30-4-1943 (surroundings of Auschwitz, the last day of April). The list is one of many. This sheet was typed on 29 April 1959. It covers the letter A through the start of B.
Concentratiekamp · Lijst No. 1908 · Frank (A–Ba), page 14 Typed list of Dutch concentration-camp victims · d.d. 29-4-1959
Sources
Transport list: numbers 306, 307, 308, 309 (Margot, Otto, Edith, Anne Frank). Nederlandse Rode Kruis, Den Haag (war archive now held by the Nationaal Archief): Transportlijst Westerbork–Auschwitz, 3 september 1944 (inv. nr. 1066, Blatt 7). Otto Frank is listed at number 307 as "Frank Otto 12.5.89 Kaufman." Cited via the scholarly apparatus of the Anne Frank House Knowledge Base: Deportation to Auschwitz-Birkenau. This was the last transport from Westerbork to Auschwitz; larger transports left afterwards for other destinations, including transport XXIV/7 to Theresienstadt on 4 September 1944 with over 2,000 people.
Auschwitz-Birkenau: selection at the ramp, separation of men and women; arrival confirmed on the night of Tuesday 5 to Wednesday 6 September 1944. By the Anne Frank House's reconstruction from the transport list and camp number series, 648 of the 1,019 persons (399 men, 249 women) entered the camp administration and 371 were killed on arrival. Danuta Czech's Kalendarium der Ereignisse im Konzentrationslager Auschwitz-Birkenau gives the older standard figures for this transport: 470 registered (258 men, 212 women) and 549 killed. Anne Frank House Knowledge Base: Selections upon arrival at Auschwitz-Birkenau; Auschwitz I: the men in the Stammlager.
The new internal Birkenau ramp (Neue Rampe), operational from May 1944. Muzeum Auschwitz-Birkenau (Oświęcim): The unloading ramps and selections.
Auschwitz I: double barbed-wire fence, watchtowers, high-voltage electrification, and the "neutral zone" where prisoners could be shot. Wacław Długoborski, Franciszek Piper (eds.), Auschwitz 1940–1945. Central issues in the history of the camp, Oświęcim: Auschwitz-Birkenau State Museum, 2000, vol. I, and survivor testimonies. Photographs of the preserved fence system: Muzeum Auschwitz-Birkenau: Watchtowers and fence system (Former Auschwitz I site).
Otto Frank's transfer to Auschwitz I. The Anne Frank House states that the men were taken to Auschwitz I, about three kilometres away; the camp's layout and standard practice suggest they made the journey on foot. No document explicitly records the mode of travel for this group. Anne Frank House Knowledge Base: Auschwitz I: the men in the Stammlager.
Transfer of Margot and Anne to Bergen-Belsen (selected 30 October 1944; transport departed 1 November; arrived 3 November). Dates reconstructed from survivor correspondence and interviews (letters of Margot Rosenthal and Nanette Blitz to Otto Frank; Willy Lindwer, De laatste zeven maanden, 1988; synthesis in Bas von Benda-Beckmann, Na het Achterhuis, 2020); no transport list naming Anne or Margot survives. Anne Frank House Knowledge Base: Journey to Bergen-Belsen; Arrival at Bergen-Belsen.
Registration at Bergen-Belsen. Bergen-Belsen maintained a prisoner registration system; arriving prisoners were routinely registered and assigned numbers. The SS burned these records before liberation, so the specific registration of Anne and Margot is an inference from standard camp procedure, not a documented fact. Gedenkstätte Bergen-Belsen (Lower Saxony): Register of Names; The Dead of the Bergen-Belsen Concentration Camp.
Death of Anne and Margot Frank at Bergen-Belsen. No camp record documents their deaths. The place and approximate date rest on eyewitness accounts (Brilleslijper, Blitz, Van Amerongen, and others) and subsequent historical analysis. The 31 March 1945 administrative default and the February 1945 revision are discussed in Anne Frank House: Sources for the date of death of Anne and Margot Frank in Bergen-Belsen (2015): eyewitness statements, the Bergen-Belsen–Raguhn transport list of 7 February 1945 (ITS, Bad Arolsen), a Red Cross parcel receipt of c. 23 January 1945, and the clinical course of typhus. Anne Frank House Knowledge Base: Death of Anne and Margot Frank. Official date based on Lientje Brilleslijper's 22 January 1951 statement to the Nederlandse Rode Kruis (file 117266, cartotheekkaartje of the Afwikkelingsbureau Concentratiekampen); the same Anne Frank House document records her earlier statements of 11 November 1945 and 5 April 1951, and notes that Otto Frank needed the declarations for a certificate of inheritance. Official date set by the Commissie tot het doen van aangifte van overlijden van vermisten, Dutch Ministry of Justice. Underlying archival research: Raymund Schütz, Vermoedelijk op transport (Master's thesis, Archival Science, Universiteit Leiden Instituut Geschiedenis, 2010).
Edith Frank-Holländer: death at Auschwitz II–Birkenau, 6 January 1945. The place and date rest solely on the account of Rosa de Winter-Levy; no camp record confirms them. See also the Anne Frank House Knowledge Base.
Westerbork transit camp: site memorial and documentation. Herinneringscentrum Kamp Westerbork (Hooghalen): kampwesterbork.nl.
Westerborkregister: extract card for Annelies Marie Frank, transport of 3 September 1944. Pink preprinted card citing the Westerbork register (Blz. 40) and recording surname (Frank), given names (Annelies, M.), date of birth (12-6-29), home address (Merwedeplein 37, Amsterdam), and transport date (3-9-44). Preserved in Anne Frank's overlijdensdossier at the Committee; the card's own production date is not established. The oldest documents in the dossier are the Committee's forms of 6 April 1951, so the card was most likely made in the course of postwar processing rather than at the camp. Nationaal Archief, Den Haag: Ministerie van Justitie / Commissie tot het doen van aangifte van overlijden van vermisten, toegangsnummer 2.09.34.02, inv.nr. 539. Publicly accessible; no copyright restrictions ("Volledig openbaar. Er zijn geen beperkingen krachtens het auteursrecht").
Aangifte van overlijden van vermiste (declaration of death of a missing person): Annelies Marie Frank, No. 107,658. Issued in 's-Gravenhage (The Hague) on 29 July 1954 by the Commissie tot het doen van aangifte van overlijden van vermisten (Ministry of Justice), a body established under the Wet van 2 Juni 1949 (Stbl. No. J 227) to produce paper closure for Dutch residents missing from the war. Entered by the Amsterdam civil registrar on 29 October 1954 in the Register van Overlijden, Register A 105, Folio 9. Nationaal Archief, Den Haag: toegangsnummer 2.09.34.02, inv.nr. 539. Publicly accessible; no copyright restrictions. The same document is catalogued at Yad Vashem, Record Group O.41, item 5222601. The full chronology of the Committee's handling of Anne Frank's case (6 April 1951 inquiries to the Dutch Red Cross and Amsterdam civil registrar; Kleiman's 7 May 1954 letter on behalf of Otto Frank; the Committee's 4 June 1954 acknowledgment; the 29 July 1954 declaration; the 29 October 1954 Amsterdam registration) is set out in the Nationaal Archief's public exhibition page, Het overlijden van Anne Frank wordt vastgesteld.
Cartotheekkaartje: NRK Information Bureau conclusion card, stamped 22 January 1952. Handwritten index card summarising Brilleslijper's statement and establishing the administrative bracket for the date of death: Overleden te Bergen-Belsen niet eerder dan op 1.3.45 en uiterlijk 31.3.45. References NRK Information Bureau Report 6/XIV No. 102, Opsporing Joodse Personen (Search for Jewish Persons). Preserved in Anne Frank's persoonsdossier at the Dutch Red Cross Information Bureau. Nationaal Archief, Den Haag: Het Nederlandse Rode Kruis — Informatiebureau: Persoonsdossiers, toegangsnummer 2.19.288, inv.nr. 101677 (persoonsdossier Anne Frank, vervroegd openbaar gemaakt / released ahead of schedule, October 2023).
Archiefkaart: Frank, Annelies Marie. Amsterdam civil registry reference card citing the overlijdensakte at Register A 105, Folio 9, d.d. 29-10-1954. The Stadsarchief Amsterdam holds archief- and persoonskaarten under toegangsnummer 30238, and cards of deceased persons are publicly accessible online at archief.amsterdam. The archival provenance of the specific scan reproduced above is not established here.
Typed concentration-camp victim list reproduced above. Header: CONCENTRATIEKAMP — Lijst No. 1908. Column headers: Naam / Voornaam / Plaats en datum van geboorte / Plaats en datum van overlijden. Page 14 of a larger series; typed footer dated 29 April 1959, with bilingual Dutch-French labels par typ and par contr. The format is consistent with Nederlandse Rode Kruis compilations from the postwar Afwikkelingsbureau Concentratiekampen, but the archival provenance of the scan itself is not established here.
Provenance · Integrity Record
Canonical processed file hashes · SHA‑512
Hash is of the byte-identical JPEG converted from raw sensor data. Verify with sha512sum -c SHA512SUMS.
The DE1-SoC from Terasic is an excellent board for hardware design and prototyping. The following VHDL process is from a hardware design created for the Terasic DE1-SoC FPGA. The ten switches and four buttons on the FPGA are used as an n-bit counter with an adjustable multiplier to increase the output frequency of one or more output pins at a 50% duty cycle.
As the switches are moved or the buttons are pressed, the seven-segment display is updated to reflect the numeric output frequency, and the output pin(s) are driven at the desired frequency. The onboard clock runs at 50MHz, and the signal on the output pins is set on the rising edge of the clock input signal (positive edge-triggered). At 50MHz, the output pins can be toggled at a maximum rate of 50 million cycles per second or 25 million rising edges of the clock per second. An LED attached to one of the output pins would blink 25 million times per second, not recognizable to the human eye. The persistence of vision, which is the time the human eye retains an image after it disappears from view, is approximately 1/16th of a second. Therefore, an LED blinking at 25 million times per second would appear as a continuous light to the human eye.
scaler <= compute_prescaler((to_integer(unsigned( SW )))*scaler_mlt); gpiopulse_process : process(CLOCK_50, KEY(0)) begin if (KEY(0) = '0') then -- async reset count <= 0; elsif rising_edge(CLOCK_50) then if (count = scaler - 1) then state <= not state; count <= 0; elsif (count = clk50divider) then -- auto reset count <= 0; else count <= count + 1; end if; end if; end process gpiopulse_process;
The scaler signal is calculated using the compute_prescaler function, which takes the value of a switch (SW) as an input, multiplies it with a multiplier (scaler_mlt), and then converts it to an integer using to_integer. This scaler signal is used to control the frequency of the pulse signal generated on the output pin.
The gpiopulse_process process is triggered by a rising edge of the CLOCK_50 signal and a push-button (KEY(0)) press. It includes an asynchronous reset when KEY(0) is pressed.
The count signal is incremented on each rising edge of the CLOCK_50 signal until it reaches the value of scaler - 1. When this happens, the state signal is inverted and count is reset to 0. If count reaches the value of clk50divider, it is also reset to 0.
Overall, this code generates a pulse signal with a frequency controlled by the value of a switch and a multiplier, which is generated on a specific output pin of the FPGA board. The pulse signal is toggled between two states at a frequency determined by the scaler signal.
It is important to note that concurrent statements within an architecture are executed concurrently, meaning that they are evaluated concurrently and in no particular order. However, the sequential statements within a process are executed sequentially, meaning that they are evaluated in order, one at a time. Processes themselves are executed concurrently with other processes, and each process has its own execution context.
The 96boards CE specification calls for an optional JTAG connection. The specification also indicates that the optional JTAG connection shall use a 10 pin through hole, .05" (1.27mm) pitch JTAG connector. The part is readily available on most electronics sites. Breaking out the pins with long wires and shrink wrapping them is ideal for making sure that each connection is labeled and separate when connecting to a JTAG debugger. While a JTAG connection is not required for flashing or loading the bootloaders onto the board, the JTAG connection is useful for advanced chip-level debugging. The serial UART connection is sufficient for loading release or debug versions of bl0, bl1, bl2, bl31, bl32, the kernel, and userspace. Last but not least, ARM-powered boards, with 12V power input, often require external fans to keep the board cool. As seen in the below photos, two 5V fans were powered from an external power supply. Any work on microcontroller boards should be performed on a grounded surface. Proper grounding procedures should always be followed as most microcontroller boards contain ESD sensitive components.
In the below photos, a 96Boards SBC is mounted on an IP65, ABS plastic junction box for durability. The pins are extended and mounted with screws underneath the junction box. The electrical conduit holes on the side of the junction box are ideal for holding small, project fans. The remaining electrical conduit holes provide a clean place to place the remaining wires from the board - micro USB, USB-C, and 12V power.
The Kirin 960 SoC and on-board USB 3.0 make the HiKey 960 SBC an ideal platform for running a Linux Bridged firewall. The number of single-board computers with an SoC as powerful as the HiSilicon Kirin 960 are limited.
When compared with the Raspberry Pi series of single board computers (SBC), the HiKey 960 SBC is significantly more powerful. The Kirin 960 also stands above the ARM powered SoCs which reside in most commercial routers.
USB 3.0 makes the HiKey 960 board an attractive option for bridging or routing, filtering network traffic, or connecting to an external gateway via IPSec. Both network traffic filtering and IPSec tunneling can be computationally expensive operations. However; the multicore Kirin 960 is well suited for these types of tasks.
In order to be able to run an IPSec client tunnel and a Linux Bridged firewall connected over 1G ethernet links, certain kernel configuration modifications are needed. Furthermore, the Android Linux kernel for the HiKey 960 board does not boot on a standard Linux root filesystem because it is designed to boot an Android customized rootfs.
The latest googlesource Linux kernel (hikey-linaro-4.9) for Android (designed to boot Android on the HiKey 960 board) has been customized to remove the Android specific components so that the kernel boots on a standard Linux root filesystem, with the proper drivers enabled for network connectivity via attached 1000Mb/s USB 3.0 to ethernet adapters. The standard UART interface on the board should be used for serial connectivity and shell access. WiFi and Bluetooth have been removed from the kernel configuration. The kernel should be booted off of a microSDHC UHS-I card. The 96boards instructions should be followed for configuring the HiKey 960 board, setting the jumpers on the board, building and flashing the l-loader, firmware package, partition tables, UEFI loader, ARM Trusted Firmware, and optional Op-TEE. Links for the normal Linux kernel configuration, multi-interface bridge configuration, and single interface IPSec configuration are below. Additional kernel config modifications may be needed for certain types of applications.
kernel build instructions
mkdir /usr/local/toolchains
cd /usr/local/toolchains/
wget https://releases.linaro.org/components/toolchain/binaries/latest/aarch64-linux-gnu/gcc-linaro-7.2.1-2017.11-x86_64_aarch64-linux-gnu.tar.xz
tar -xJf gcc-linaro-7.2.1-2017.11-x86_64_aarch64-linux-gnu.tar.xz
export ARCH=arm64
export CROSS_COMPILE=/usr/local/toolchains/gcc-linaro-7.2.1-2017.11-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
export PATH=/usr/local/toolchains/gcc-linaro-7.2.1-2017.11-x86_64_aarch64-linux-gnu/gcc-aarch64-linux-gnu/bin:$PATH
cd /usr/local/src
git clone https://android.googlesource.com/kernel/hikey-linaro
cd hikey-linaro
git checkout -b android-hikey-linaro-4.9
make hikey960_defconfig
make -j8
multi-interface bridge configuration
Bridged configuration, no ip addresses on dual nic interfaces. (crossover cable is useful for testing). Bridge interface obtains dhcp address(/11) from wlan router. aliased interface added to br0 and assigned private subnet ip on different subnet (/8). Spanning tree set on bridge interface. Basic ebtables and iptables ruleset below.
brctl addbr <br>
brctl addif <br> <eth1> <eth2>
ifconfig <br> up
ifconfig <eth1> up
ifconfig <eth2> up
brctl stp <br> yes
dhclient <br>
ifconfig <br>:0 <a.b.c.d/sn> up
iptables --table nat --append POSTROUTING --out-interface <br> -j MASQUERADE
iptables -P INPUT DROP
iptables --append FORWARD --in-interface <br>:0 -j ACCEPT
ebtables -P FORWARD DROP
ebtables -P INPUT DROP
ebtables -P OUTPUT DROP
ebtables -t filter -A FORWARD -p IPv4 -j ACCEPT
ebtables -t filter -A INPUT -p IPv4 -j ACCEPT
ebtables -t filter -A OUTPUT -p IPv4 -j ACCEPT
ebtables -t filter -A INPUT -p ARP -j ACCEPT
ebtables -t filter -A OUTPUT -p ARP -j ACCEPT
ebtables -t filter -A FORWARD -p ARP -j REJECT
ebtables -t filter -A FORWARD -p IPv6 -j DROP
ebtables -t filter -A FORWARD -d Multicast -j DROP
ebtables -t filter -A FORWARD -p X25 -j DROP
ebtables -t filter -A FORWARD -p FR_ARP -j DROP
ebtables -t filter -A FORWARD -p BPQ -j DROP
ebtables -t filter -A FORWARD -p DEC -j DROP
ebtables -t filter -A FORWARD -p DNA_DL -j DROP
ebtables -t filter -A FORWARD -p DNA_RC -j DROP
ebtables -t filter -A FORWARD -p LAT -j DROP
ebtables -t filter -A FORWARD -p DIAG -j DROP
ebtables -t filter -A FORWARD -p CUST -j DROP
ebtables -t filter -A FORWARD -p SCA -j DROP
ebtables -t filter -A FORWARD -p TEB -j DROP
ebtables -t filter -A FORWARD -p RAW_FR -j DROP
ebtables -t filter -A FORWARD -p AARP -j DROP
ebtables -t filter -A FORWARD -p ATALK -j DROP
ebtables -t filter -A FORWARD -p 802_1Q -j DROP
ebtables -t filter -A FORWARD -p IPX -j DROP
ebtables -t filter -A FORWARD -p NetBEUI -j DROP
ebtables -t filter -A FORWARD -p PPP -j DROP
ebtables -t filter -A FORWARD -p ATMMPOA -j DROP
ebtables -t filter -A FORWARD -p PPP_DISC -j DROP
ebtables -t filter -A FORWARD -p PPP_SES -j DROP
ebtables -t filter -A FORWARD -p ATMFATE -j DROP
ebtables -t filter -A FORWARD -p LOOP -j DROP
ebtables -t filter -A FORWARD --log-level info --log-ip --log-prefix FFWLOG
ebtables -t filter -A OUTPUT --log-level info --log-ip --log-arp --log-prefix OFWLOG -j DROP
ebtables -t filter -A INPUT --log-level info --log-ip --log-prefix IFWLOG
single-interface ipsec gateway configuration
iptables -t nat -A POSTROUTING -s <clientip>/32 -o <eth> -j SNAT --to-source <virtualip>
iptables -t nat -A POSTROUTING -s <clientip>/32 -o <eth> -m policy --dir out --pol ipsec -j ACCEPT
XOR logic gates are a fundamental component in cryptography, and many of the typical stream and block ciphers use XOR gates. A few of these ciphers are ChaCha (stream cipher), AES (block cipher), and RSA (block cipher).
While many compiled and interpreted languages support bitwise operations such as XOR, the software implementation of both block and stream ciphers is computationally inefficient compared to FPGA and ASIC implementations.
Hybrid FPGA boards integrate FPGAs with multicore ARM and Intel application processors over high-speed buses. The ARM and Intel processors are general-purpose processors. On a hybrid board, the ARM or Intel processor is termed the hard processor system or HPS. Writing to the FPGA from the HPS is typically performed via C from an embedded Linux build (yocto or buildroot) running on the ARM or Intel core. A simple bitstream can also be loaded into the FPGA fabric without using any ARM design blocks or functionality in the ARM core for a hybrid ARM configuration.
The following is a simple hardware design written in VHDL and simulated in ModelSim. The image contains the waveform output of a simulation in ModelSim. The HPS is not used. On boot, the bitstream is loaded into the FPGA fabric. VHDL components are utilized, and a testbench is defined for testing the design. The entity and architecture VHDL design units are below.
- --three input xnor gate entity declaration - external interface to design entity entity xnorgate is port ( a,b,c : in std_logic; q : out std_logic); end xnorgate;
architecture xng of xnorgate is begin q <= a xnor b xnor c; end xng;
- --chain of xor / xnor gates using components and sequential logic entity xorchain is port ( A,B,C,D,E,F : in std_logic; Av,Bv : in std_logic_vector(31 downto 0); CLOCK_50 : in std_logic; Q : out std_logic; Qv : out std_logic_vector(31 downto 0)); end xorchain;
architecture rtl of xorchain is component xorgate is port ( a,b : in std_logic; q : out std_logic); end component;
component xnorgate is port ( a,b,c : in std_logic; q : out std_logic); end component;
component xorsgate is port ( av : in std_logic_vector(31 downto 0); bv : in std_logic_vector(31 downto 0); qv : out std_logic_vector(31 downto 0)); end component;
signal a_in, b_in, c_in, d_in, e_in, f_in : std_logic; signal av_in, bv_in : std_logic_vector(31 downto 0);
signal conn1, conn2, conn3 : std_logic;
begin xorgt1 : xorgate port map(a => a_in, b => b_in, q => conn1); xorgt2 : xorgate port map(a => c_in, b => d_in, q => conn2); xorgt3 : xorgate port map(a => e_in, b => f_in, q => conn3); xnorgt1 : xnorgate port map(conn1, conn2, conn3, Q); xorsgt1 : xorsgate port map(av => av_in, bv => bv_in, qv => Qv);
process(CLOCK_50) begin if rising_edge(CLOCK_50) then --assign inputs on rising clock edge a_in <= A; b_in <= B; c_in <= C; d_in <= D; e_in <= E; f_in <= F; av_in(31 downto 0) <= Av(31 downto 0); bv_in(31 downto 0) <= Bv(31 downto 0); end if;
end process; end rtl;
entity xorchain_tb is end xorchain_tb;
architecture xorchain_tb_arch of xorchain_tb is signal A_in,B_in,C_in,D_in,E_in,F_in : std_logic := '0'; signal Av_in : std_logic_vector(31 downto 0); signal Bv_in : std_logic_vector(31 downto 0); signal CLOCK_50_in : std_logic; signal BRK : boolean := FALSE; signal Q_out : std_logic; signal Qv_out : std_logic_vector(31 downto 0);
component xorchain port ( A,B,C,D,E,F : in std_logic; Av : in std_logic_vector(31 downto 0); Bv : in std_logic_vector(31 downto 0); CLOCK_50 : in std_logic; Q : out std_logic; Qv : out std_logic_vector(31 downto 0)); end component;
begin xorchain_instance: xorchain port map (A => A_in,B => B_in, C => C_in, D => D_in, E => E_in, F => F_in, Av => Av_in, Bv => Bv_in, CLOCK_50 => CLOCK_50_in, Q => Q_out, Qv => Qv_out); clockprocess: process begin while not BRK loop CLOCK_50_in <= '0'; wait for 20 ns; CLOCK_50_in <= '1'; wait for 20 ns; end loop; wait; end process clockprocess;
testprocess : process begin A_in <= '1'; B_in <= '0'; C_in <= '1'; D_in <= '0'; E_in <= '1'; F_in <= '1'; wait for 40 ns; A_in <= '1'; B_in <= '0'; C_in <= '1'; D_in <= '0'; E_in <= '1'; F_in <= '0'; wait for 20 ns; A_in <= '0'; B_in <= '0'; C_in <= '1'; D_in <= '0'; E_in <= '1'; F_in <= '0'; wait for 40 ns; BRK <= TRUE; wait; end process testprocess; end xorchain_tb_arch;
entity xorgate is port ( a,b : in std_logic; q : out std_logic); end xorgate;
architecture xg of xorgate is begin q <= a xor b; end xg;
entity xorsgate is port ( av : in std_logic_vector(31 downto 0); bv : in std_logic_vector(31 downto 0); qv : out std_logic_vector(31 downto 0)); end xorsgate;
architecture xsg of xorsgate is begin qv <= av xor bv; end xsg;
GNURadio Companion Qt Gui Frequency Sync - multiple FIR filter taps sample running on Raspberry Pi 3 custom Linux distribution
The Raspberry Pi 3 is powered by the ARM Cortex-A53 processor. This 1.2GHz 64-bit quad-core processor fully supports the ARMv8-A architecture. For this project, a custom Linux distribution was created for the Raspberry Pi 3.
The custom Linux distribution includes support for GNURadio, several FPGA and ARM Powered SDR devices, D-STAR (hotspot, repeater, and dongle support), hsuart, libusb, hardware real-time clock support, Sony 14 megapixel NoIR image sensor, HDMI and 3.5mm audio, USB Microphone input, X-windows with Xfce, Lighttpd and PHP, Bluetooth, WiFi, SSH, TCPDump, Docker, Docker registry, MySQL, Perl, Python, QT, GTK, IPTables, x11vnc, SELinux, and full native-toolchain development support.
The Sony 14 megapixel image sensor with the infrared filter removed can be connected to the Raspberry Pi 3's MIPI camera serial interface. Image capture and recognition can then be performed over contiguous periods of time, and time-lapsed video can be created from the images. With support for Tensorflow and OpenCV, object recognition within images can be performed.
D-STAR hotspot with time-lapsed infrared imaging.
For the initial run, an infrared Time-lapse Video was created from an initial image capture run of one 3280x2460 infrared jpeg image captured every 15 seconds for three hours. 40, 5mm, 940nm LEDs, powered by 500ma over 12v DC, provided infrared illumination in the 940nm wavelength.
Tensorflow ran in the background (on v4l2 kmod) and provided continuous object recognition and scoring within each image via a sample model. Finally, OpenCV was also installed in the root file system.
The time-lapse infrared video was captured of the living room using the above setup. Below this image are images of Tensorflow running in a terminal in the background on the Raspberry Pi 3 and recognizing/scoring objects in the living room.
Tensorflow running on the Raspberry Pi 3 and continuously capturing frames from the image sensor and scoring objects
GNURadio Companion running on xfce on the Raspberry Pi 3
The ARM DS-5 Streamline Performance Analyzer is a powerful tool for debugging, profiling, and analyzing multithreaded and multiprocess C programs. Instructions can easily be traced between load and store operations. Per process and per thread function call paths can be broken down by system utilization percentage. Branch mispredictions and multi-level CPU caches can be analyzed. Furthermore, disk I/O usage, stack and heap usage, and a number of other useful metrics can quickly be referenced within the debugger. These are just a few of its capabilities.
In order to capture meaningful information from the DS-5 Streamline Performance Analyzer tool, a Linux, multiprocess, C program was modified to insert 1000 packets into a packet processing simulation buffer. A code excerpt from the program is below. The child processes were modified to sleep and then wake 1000 times in order to simulate process activity. The program was analyzed using the DS-5 Streamline Performance Analyzer tool. There are two screenshots below the code excerpt where the program is loaded into the DS-5 Streamline Performance Analyzer.
void *insertpackets(void *arg) {
struct pktbuf *pkbuf; struct packet *pkt; int idx;
if(arg != NULL) {
pkbuf = (struct pktbuf *)arg;
/* seed random number generator */ ...
/* insert 1000 packets into the packet buffer */ for(idx = 0; idx < 1000; ++idx) {
DE1-SoC GPIO Pins connected to 780nm Infrared Laser Diodes, 660nm Red Laser Diodes, and Oscilloscope
The following VHDL processes pulse the GPIO pins at different frequencies on the Altera DE1-SoC using multiple Phase-Locked Loops. Several diodes were connected to the GPIO banks and pulsed at a 50% duty cycle with 16mA across 3.3V. Each GPIO bank on the DE1-SoC has 36 pins. Pin 1 is pulsed at 20Hz from GPIO bank 0, and pins 0 and 1 are pulsed at 30Hz from GPIO bank 1. A direct mode PLL with locked output was configured using the Altera Quartus Prime MegaWizard. The PLL reference clock frequency is set to 50MHz, the output clock frequency is set to 50MHz, and the duty cycle is set to 50%. The pin mappings for GPIO banks 0 and 1 are documented on the DE1-SoC datasheet.
Pulsed Laser Diodes via GPIO pins on DE1-SoC FPGA
- -- --------------------- - -- CLOCK A AND B PROCESSES -- - -- INPUT: direct mode pll with locked output - -- and reference clock frequency set to 50MHz, - -- output clock frequency set to 50MHz with 50% duty - -- cycle and output frequency scaled by freq divider constant - -- -----------------------------------------------------------
clk_a_process : process (lkd_pll_clk_a) begin if rising_edge(lkd_pll_clk_a) then if (cycle_ctr_a < FREQ_A_DIVIDER) then cycle_ctr_a <= cycle_ctr_a + 1; else cycle_ctr_a <= 0; end if; end if; end process clk_a_process;
clk_b_process : process (lkd_pll_clk_b) begin if rising_edge(lkd_pll_clk_b) then if (cycle_ctr_b < FREQ_B_DIVIDER) then cycle_ctr_b <= cycle_ctr_b + 1; else cycle_ctr_b <= 0; end if; end if; end process clk_b_process;
- -- --------------------- - -- GPIO A AND B PROCESSES -- - -- INPUT: direct mode pll with locked output - -- ------------------------------------------------------- gpio_a_process : process (lkd_pll_clk_a) begin if rising_edge(lkd_pll_clk_a) then if (cycle_ctr_a = 0) then gpio_sig_0 <= NOT gpio_sig_0; end if; end if; end process gpio_a_process;
gpio_b_process : process (lkd_pll_clk_b) begin if rising_edge(lkd_pll_clk_b) then if (cycle_ctr_b = 0) then gpio_sig_1 <= NOT gpio_sig_1; end if; end if; end process gpio_b_process; GPIO_0 <= gpio_sig_0; GPIO_1 <= gpio_sig_1;
The DE1-SoC FPGA Development board from Terasic is powered by an integrated Altera Cyclone V FPGA and ARM MPCore Cortex-A9 processor. The FPGA and ARM core are connected by a high-speed interconnect fabric. Linux can be booted on the ARM core and the FPGA and ARM core can communicate.
The DE1-SoC board below has been programmed via Quartus Prime running on Fedora 23, 64-bit Linux. The FPGA bitstream was compiled from the Terasic Audio codec design reference. After the bitstream was loaded on to the FPGA over the USB blaster II interface, the NIOS II command shell was used to load the NIOS II software image onto the chip. A menu-driven, debug interface is running from a terminal on the host via the NIOS II shell with the target connected over the USB Blaster II interface.
A low-level hardware abstraction layer was programmed in C to configure the on-board audio codec chip. The NIOS II chip is stored in on-chip memory and a PLL driven, clock signal is fed into the audio chip. The Verilog code for the hardware design was generated from Qsys. The design supports configurable sample rates, mic in, and line in/out.
Additional components are connected to the DE1-SoC board in this photo. The Linear DC934A (LTC2607) DAC is connected to the DE1-SoC and an oscilloscope is connected to the ground and vref pins on the DAC.
The DC934A features an LTC2607 16-Bit Dual DAC with i2c interface and an LTC2422 2-Channel 20-Bit uPower No Latency Delta Sigma ADC.
3.5mm audio cables are connected to the mic in and line out ports, respectively. The DE1-SoC is connected to an external display over VGA so that a local console can be managed via a connected keyboard and mouse when Linux is booted from uSD.
With GPIO pins accessible via the GPIO 0 and 1 breakouts, external LEDs can be pulsed directly from the Hard Processor System (HPS), FPGA, or the FPGA via the HPS.
Understanding the boot loader on a computer system is probably the most important aspect of security. Most computer systems have multiple boot loaders that run in sequence immediately after a power reset is applied to the processor on the computer system. This applies to embedded, desktop, and server systems.
The Altera Cyclone V SoC has an FPGA and a Hard Processor System (HPS) woven into a single processor package. The HPS is a dual core ARM Cortex A9. Building everything from scratch is the best way to figure out how the system works.
The boot sequence on a Cyclone V HPS works like this:
The On-chip ROM (for which source code is not provided) loads the preloader (1st stage bootloader). The preloader then loads U-boot. U-boot then loads the kernel and root file system.
There are two well thought out options for the preloader according to the Cyclone V boot guide. The two options are licensed differently depending on how the source code is built. One is licensed under a BSD license and the other under GPL v2 with U-Boot.
Building a pre-loader image for the DE0-Nano-SoC board was straightforward. Altera provides the bsp-editor utility for customizing the preloader configuration and generating the BSP HPS preloader source code, after which, make is used to build the sources using the Mentor ARM cross toolchain. The preloader settings directory can be found on the DE0-Nano-SoC CD in the DE0_NANO_SOC_GHRD subdirectory.
The preloader load address can be set via the bsp-editor so that the on chip ROM either loads the preloader from an absolute zero address on the sdcard or from a fat partition with id equal to a2 on the sdcard. These are the options for booting from the sdcard.
After the sources are generated and the preloader image is built using the Makefile, U-boot must be compiled. An Altera port of U-Boot is available on github for the Cyclone V FPGA SoC. U-Boot is built using the Linaro ARM cross toolchain.
There's quite a bit that can be done with the Cyclone V FPGA SoC boot configuration. FPGA images can be loaded from U-boot. The jumpers on the board can be configured to boot from the on-board serial flash (QSPI), bare metal applications can be loaded from the preloader, the FPGA can be configured from serial flash, and the list goes on. The HPS SoC Boot Guide for the Cyclone V SoC is a valuable reference and contains all of the boot configuration information.
The NE555 timer IC is a classic and widely used component in electronic circuits, so building a transistor-scale replica of it is a great way to understand how it works at a fundamental level. It's also a good way to develop your soldering skills and learn how to use an oscilloscope to measure signals in a circuit.
I picked up a "Three Fives" Discrete Timer Kit this weekend. As it turns out the kit was well worth the money. The "Three Fives" Discrete Timer Kit is a transistor-scale replica of the NE555 timer IC. The printed circuit board (PCB) is high-quality and soldering the transistors and resistors was alot of fun. Thanks to Eric Schlaepfer and Evil Mad Scientist Labs for this high quality circuit kit.
The size of the board makes it easy to measure what's going on inside the circuit. Just connect the probes from an oscilloscope to any of the solder or test points on the board.
A photo of the board that I built is below. I also wired a sample test circuit for blinking a pink LED and then connected a scope to the board so that I could look at the square wave.
In part III of this guide, the installation of the final image to the SD card will be covered. The SD card will then be booted on the target. Finally, audio recording and playback will be tested.
Part III of this guide consists of the following sections.
Write the GNU/Linux BSP image to an SD card.
Set the physical switches on the RioTboard (Internet of Things) to boot from the uSD or SD card.
Connect the target to the necessary peripherals for boot.
Test audio recording, audio playback, and Internet connectivity.
1. Write the GNU/Linux BSP image to an SD card
At this point, the build should be complete, without errors. The output should be as follows.
real254m28.335s user737m9.307s sys133m39.529s
Insert an SD card into an SD card reader, connect it to the host, and execute the following commands on the host.
2. Set the physical switches on the RioTboard to boot from the uSD or SD card.
For booting from the SD card on the bottom of the target, set the physical switches as follows.
SD (J6, bottom) 1 0 1 0 0 1 0 1
For booting from the uSD card on the top of the target, set the physical switches as follows.
uSD (J7, top) 1 0 1 0 0 1 1 0
3. Connect the target to the necessary peripherals for boot.
There are two options
Option 1
Connect one end of an ethernet cable to the target. Connect the other end of the ethernet cable to a hub or DHCP server.
Connect the board to the host computer via the J18 serial UART pins on the target. This will require a serial to USB breakout cable. Connect TX, RX, and GND to RX, TX, and GND on the cable. The cable must have an FTDI or similar level shifter chip. Connect the USB end of the cable to the host computer.
Connect the speakers to the light green 3.5 mm audio out jack and the microphone to the pink 3.5 mm MIC In jack.
Connect a 5V / 4 AMP DC power source to the target.
Run minicom on the host computer. Configure minicom at 115200 8N1 with no hardware flow control and no software flow control. If a USB to serial cable with an FTDI chip in it is used, then the cable should show up in /dev as ttyUSB0 in which case, set the serial device in minicom to /dev/ttyUSB0.
If this option was chosen, drop into U-boot after power on by pressing Enter on the host keyboard with minicom open and connected.
If enter is not pressed after power-on, the target will boot and a login prompt will appear.
A login prompt will not appear.
Option 2
Connect one end of an ethernet cable to the target. Connect the other end of the ethernet cable to a hub or DHCP server.
Connect a USB keyboard, USB mouse, and monitor (via an HDMI cable) to the target.
Connect the speakers to the light green 3.5 mm audio out jack and the microphone to the pink 3.5 mm MIC In jack.
Connect a 5V / 4 AMP DC power source to the target.
A login prompt will now appear.
4. Test audio recording, audio playback, and Internet connectivity
Type root to log in to the target. The root password is not set.
Execute the following commands on the target
root@imx6dl-riotboard: alsamixer
Press F6. Press arrow down so that 0 imx6-riotboard-sgtl5000 is highlighted. Press Enter. Increase Headphone level to 79<>79. Increase PCM level to 75<>75. Press Tab. Increase Mic level to 59. Increase Capture to 80<>80. Press Esc.
root@imx6dl-riotboard: cd /usr/share/alsa/sounds root@imx6dl-riotboard: aplay *.wav
A sound should be played through the speakers.
root@imx6dl-riotboard: cd /tmp root@imx6dl-riotboard: arecord -d 10 micintest.wav
