Thursday, February 1, 2018

a Hardware Design for XOR gates using sequential logic in VHDL

Hybrid boards with ARM processors integrate FPGAs with multicore ARM processors over high speed buses.  The ARM processor is termed the hard processor system or HPS.  Writing to the FPGA from the ARM processor is typically performed via C from an embedded Linux build (yocto or buildroot) running on the ARM core.  A simple bitstream can also be loaded into the FPGA fabric without using any ARM design blocks or functionality in the ARM core.

ModelSim Wave Output for the xor design
The following is a simple hardware design that I wrote in VHDL and subsequently simulated in ModelSim.  The HPS is not used. The bitstream is loaded into the FPGA fabric on boot.  The sequential design is comprised of several XOR gates, XNOR'd together with a 50Mhz input clock. XOR gates are common in cryptography.  VHDL components are utilized and a testbench is defined for testing the design.  The testbench for the design was loaded into ModelSim and the below image is the wave form simulation of the input signals, clock, and output signal.

The source code is available on github at the following link.
xorchain hardware design in VHDL

ModelSim Full Window view with wave form output of xor simulation. ModelSim-Intel FPGA Starter Edition © Intel