Thursday, February 1, 2018

a Hardware Design for XOR gates using sequential logic in VHDL

VHDL is a powerful, hardware description language.  The learning curve is steep and advanced hardware designs take many years of experience.  As an advanced C and C++ programmer with embedded hardware experience, I decided to take on the task of learning VHDL.  An FPGA board is typically needed if you intend to load your design onto a re-programmable piece of hardware.  There are many choices, from simple to complex, and from cheap to very expensive.

A few years ago, a friend recommended that I purchase an FGPA board without a hybrid ARM core to start with, as working with an FPGA board is already complicated.  Having worked with numerous ARM processors, I decided to instead purchase an FPGA board with a multicore ARM processor.  Hybrid boards such as these integrate the FPGA fabric with an ARM processor, typically multicore, over a high speed bus.  For such a configuration, the ARM processor is termed the hard processor system or HPS.  Writing to the FPGA from the ARM processor is typically performed via C from an embedded Linux  build (yocto or buildroot) running on the ARM core.

ModelSim Wave Output for the xor design
The following is a simple hardware design that I wrote and simulated in ModelSim.  Given the frequency of XOR gates in cryptography, I decided to build a simple design using XOR gates.  The sequential design is comprised of several XOR gates, XNOR'd together with a 50Mhz input clock.  VHDL components are utilized and a testbench is defined for testing the design.  The testbench for the design was loaded into ModelSim and the below image is the wave form simulation of the input signals, clock, and output signal.

The source code is available on github at the following link.
xorchain hardware design in VHDL

ModelSim Full Window view with wave form output of xor simulation. ModelSim-Intel FPGA Starter Edition © Intel