Monday, June 13, 2016

VHDL Processes for Pulsing Multiple Lasers at Different Frequencies on Altera FPGA


DE1-SoC GPIO Pins connected to 780nm Infrared Laser Diodes, 660nm Red Laser Diodes, and Oscilloscope

The following VHDL processes pulse the GPIO pins at different frequencies on the Altera DE1-SoC using multiple Phase-Locked Loops.  Multiple Infrared Laser Diodes are connected to the GPIO banks and pulsed at a 50% duty cycle with 16mA across 3.3V.  Each GPIO bank on the DE1-SoC has 36 pins. Pin 1 is pulsed at 20hz from GPIO bank 0, and pins 0 and 1 are pulsed at 30hz from GPIO bank 1.  A direct mode PLL with locked output was configured using the Altera Quartus Prime MegaWizard.  The PLL reference clock frequency is set to 50mhz, the output clock frequency is set to 50mhz, and the duty cycle is set to 50%.  The pin mappings for GPIO banks 0 and 1 are documented on the DE1-SoC datasheet.

Pulsed Laser Diodes via GPIO pins on DE1-SoC FPGA

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

- --Copyright (C) 2016. Bryan R. Hinton
- --All rights reserved.
- --
- --Redistribution and use in source and binary forms, with or without
- --modification, are permitted provided that the following conditions
- --are met:
- --1. Redistributions of source code must retain the above copyright
- --   notice, this list of conditions and the following disclaimer.
- --2. Redistributions in binary form must reproduce the above copyright
- --   notice, this list of conditions and the following disclaimer in the
- --   documentation  and/or other materials provided with the distribution.
- --3. Neither the names of the copyright holders nor the names of any
- --   contributors may be used to endorse or promote products derived from this
- --   software without specific prior written permission.
- --
- --THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- --AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- --IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- --ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
- --LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- --CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- --SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- --INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- --CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- --ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- --POSSIBILITY OF SUCH DAMAGE.

- ---------------------
- -- CLOCK A PROCESS --
- ---------------------
- -- INPUT: direct mode pll with locked output 
- -- and reference clock frequency set to 50mhz, 
- -- output clock frequency set to 50mhz with 50% duty 
- -- cycle and output frequency scaled by freq divider constant
- -------------------------------------------------------------
clk_a_process : process (lkd_pll_clk_a)
begin
 if rising_edge(lkd_pll_clk_a) then
  if (cycle_ctr_a < FREQ_A_DIVIDER) then
   cycle_ctr_a <= cycle_ctr_a + 1;
  else
   cycle_ctr_a <= 0;
  end if;
 end if;
end process clk_a_process;
 
- ---------------------
- -- CLOCK B PROCESS --
- ---------------------
- -- INPUT: direct mode pll with locked output 
- -- and reference clock frequency set to 50mhz, 
- -- output clock frequency set to 50mhz with 50% duty 
- -- cycle and output frequency scaled by freq divider constant
- -------------------------------------------------------------
clk_b_process : process (lkd_pll_clk_b)
begin
      if rising_edge(lkd_pll_clk_b) then
  if (cycle_ctr_b < FREQ_B_DIVIDER) then
   cycle_ctr_b <= cycle_ctr_b + 1;
  else
   cycle_ctr_b <= 0;
          end if;
     end if;
end process clk_b_process;
 
- ---------------------
- -- GPIO A PROCESS --
- ---------------------
- -- INPUT: direct mode pll with locked output
- --------------------------------------------------------- 
gpio_a_process : process (lkd_pll_clk_a)
begin
 if rising_edge(lkd_pll_clk_a) then
         if (cycle_ctr_a = 0) then
   -- toggle gpio pin1 from gpio_0
   gpio_sig_0(1) <= NOT gpio_sig_0(1);
          end if;
       end if;
end process gpio_a_process;

- ---------------------
- -- GPIO B PROCESS --
- ---------------------
- -- INPUT: direct mode pll with locked output
- ---------------------------------------------------------
gpio_b_process : process (lkd_pll_clk_b)
begin
 if rising_edge(lkd_pll_clk_b) then
         if (cycle_ctr_b = 0) then
   -- toggle gpio pins 0 and 1 from gpio_1
   gpio_sig_1 <= NOT gpio_sig_1(1 downto 0);
          end if;
       end if;
end process gpio_b_process;
 
GPIO_0 <= gpio_sig_0;
GPIO_1 <= gpio_sig_1;

end gpioarch;
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1

iQIcBAEBAgAGBQJXX2UDAAoJEPbndIT4b5KAnYYP/RgR8RGP7JPgC6CIO+gCQxe7
QXrRV7ea9vZCSuF5stCVY1UbEOfSv2jcufUc5Bg12Ddi+d9NLLPJa4/jL+ZRtwet
G+sIGcmxmviBReQCU6zVWOyPBzwoD3EJJdkHf1KtZUmq3pJKNsYefKzqIyzfhJ3t
mOtShH1mCMqxA4RD8wqfGmA1V1U3kOGd3APWnby1MKvbWaDLbNptZLovtweaw3F5
zgNDOMdCwFZpMScVHCW2tiZyoFHnMyhPes7uaBgj3CAQLRgIVKr7jUnU6HIWh4Ag
6be78TT22Zmf32+udQHzKjKcoYpMVatuBX6zY+sJ8jY92PypDi7u0wtHt+G3Hrht
XUW69s3tjR4JWw4qFX+JSYl8b2sEzDEeGAMJeB9r0+mCUH5C3f1cNWp5k1Rsne3z
3djluxQJzzZ+icvYrVz50sQyzqx1TCNJIW7tY3Va5kjF/jmH7ubbGP9YkPy5uoKt
ZNyI971A4KC5haov4PiRA8J7aUG+hNkhadY1YI8AIoP5zlk1im7vahE44SVA777r
ATLj64gzHoVdOSsEqY9ju68XBNvLDWeyN4u4AQD/yiW+9dnD324q3jan9Vx+6jWX
Y6LYmR/6HOPb7yPGw/4W11oDZ3RwfnBCrmuUYzYWC2Y0NuDebrskzTM2tXXU3gyq
qUWJiP6qmL/nsf72nBa1
=nJWe
-----END PGP SIGNATURE-----


DE1-SoC GPIO Bank 0 Pin 1

DE1-SoC GPIO Bank 1 Pins 0 and 1

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