Thursday, February 1, 2018

a Hardware Design for XOR gates using sequential logic in VHDL

VHDL is a powerful, hardware description language.  The learning curve is steep and advanced hardware designs take many years of experience.  As an advanced C and C++ programmer with embedded hardware experience, I decided to take on the task of learning VHDL.  An FPGA board is typically needed if you intend to load your design onto a re-programmable piece of hardware.  There are many choices, from simple to complex, and from cheap to very expensive.

A few years ago, a friend recommended that I purchase an FGPA board without a hybrid ARM core to start with, as working with an FPGA board is already complicated.  Having worked with numerous ARM processors, I decided to instead purchase an FPGA board with a multicore ARM processor.  Hybrid boards such as these integrate the FPGA fabric with an ARM processor, typically multicore, over a high speed bus.  For such a configuration, the ARM processor is termed the hard processor system or HPS.  Writing to the FPGA from the ARM processor is typically performed via C from an embedded Linux  build (yocto or buildroot) running on the ARM core.

ModelSim Wave Output for the xor design
The following is a simple hardware design that I wrote and simulated in ModelSim.  Given the frequency of XOR gates in cryptography, I decided to build a simple design using XOR gates.  The sequential design is comprised of several XOR gates, XNOR'd together with a 50Mhz input clock.  VHDL components are utilized and a testbench is defined for testing the design.  The testbench for the design was loaded into ModelSim and the below image is the wave form simulation of the input signals, clock, and output signal.

The source code is available on github at the following link.
xorchain hardware design in VHDL

ModelSim Full Window view with wave form output of xor simulation. ModelSim-Intel FPGA Starter Edition © Intel

Saturday, April 29, 2017

Huawei's Powerful ARM® - The HiKey 960 Android Reference Board

Announced by Linaro on 25 April, 2017 under the 96Boards product line, the new HiKey 960 Single board computer (SBC) will power the Android and Maker ecosystems for the foreseeable future.

Designed and powered by the world's leading technology companies, Google and Huawei, the HiKey 960 is the new flagship platform for Android and embedded development.  The development of the HiKey 960 Single Board Computer (SBC) is a partnership between Linaro members ARM, Google, Huawei, Archermind, and LeMaker.

The HiKey 960 is built on HiSilicon's (an Huawei Company) powerful ARM®, the Kirin 960 Octa-core SoC. The Kirin 960 is built on the ARM®v8-a architecture and supports Big.LITTLE™ technology.  The SoC contains four ARM® Cortex®-A73 cores, four Cortex®-A53 cores, and a Mali-G71 MP8 GPU. 

The board has 3GB of LPDDR4 SDRAM memory, 32GB of UFS 2.0 flash storage, two and four lane MIPI CSI interfaces, 1080p HDMI and MIPI DSI video interfaces, I2C, SPI, GPIO, PCIe Gen2, WiFI, and Bluetooth 4.1 interfaces.  The board runs on a 12V/2A power supply which is standard for most real-world boards.  

The HiKey 960 is certified by Google and Linaro's 96Boards division.  Google certified the board for official AOSP development and 96Boards certified it under their Consumer Edition (CE) specification.

The HiKey 960 board is an ideal platform for many different types of users. Here are just a few.
  • an AOSP developer or engineer who needs a reference platform for development
  • a mobile test engineer at a telco
  • a mobile security professional
  • a person with the need to upgrade the Raspberry Pi for a more stable platform
  • a Linux kernel developer
  • a hardware engineer
  • a maker or independent developer
  • a developer involved in robotics, digital signage, or point of sale (POS)
  • a developer interested in building ARM® Trusted Firmware (ATF)
  • a platform for understanding how Android properly communicates with an underlying hardware design

If you have not purchased one yet, you can today through the following distribution channels:

Sunday, February 12, 2017

Setting up a D-Star Access Point on Raspbian with PIXEL - Part II

This is part II of a two Part series. In part I, DStarRepeater and IRCDDBGateway were compiled and DstarRepeater was configured on Raspbian Jessie with PIXEL.  In Part II, IRCDDBGateway will be configured,and an Icom ID-51a+ will connect to the D-Star network through the D-Star hotspot.

Elizabeth Tower at the North end of the Palace of Westminster in London



Configure ircddbgateway

Execute ircddbgatewayconfig on the target (Raspberry Pi) as follows.

pi@hbox:~ $ sudo ircddbgatewayconfig &

Replace KF5SVQ with your call sign.

Make sure that you select Save from the File Menu in order to save your changed to the configuration file.   Also make sure that you select Exit from the File menu after you select Save.

Start ircddbgateway and dstarrepeater

pi@hbox:~ $ sudo ircddbgateway &
pi@hbox:~ $ sudo dstarrepeater &

Configure the Radio 

Link to the UK D-Star Megarepeater

D-Pad -> Repeater List -> Simplex -> 145.67 DV
Press PTT
D-Pad -> Local CQ
Hold Down PTT and Talk

Setting up a D-Star Access Point on Raspbian with PIXEL - Part I

This is part I of a two Part series. In part I, DStarRepeater and IRCDDBGateway will be compiled and DStarRepeater will be configured on Raspbian Jessie with PIXEL.  In Part II, IRCDDBGateway will be configured and an Icom ID-51a+ will connect to the D-Star network through the D-Star hotspot.


Create a hotspot or access point for a handheld radio in order to connect to the D-Star network.



Host - Your Desktop computer (Linux)
Target - Raspberry Pi 3 running Raspbian Jessie with PIXEL (Linux)


Write the Raspbian image to the uSD on the host.  Execute the following commands on the host.

dev@fedora:~ $ sudo umount /dev/sdb*
dev@fedora:~ $ sudo dd if=2017-01-11-raspbian-jessie.img of=/dev/sdb bs=1M

Boot the Pi with the uSD card.  Execute the following commands on the Pi.

pi@hbox:~ $ apt-get install libwxgtk3.0-dev libusb-1.0-0-dev
pi@hbox:~ $ mkdir ~/src
pi@hbox:~ $ cd ~/src
pi@hbox:~ $ git clone -b master
pi@hbox:~ $ cd OpenDV/ircDDBGateway
pi@hbox:~ $ ./configure
pi@hbox:~ $ make
pi@hbox:~ $ sudo make install
pi@hbox:~ $ cd ..
pi@hbox:~ $ cd DStarRepeater
pi@hbox:~ $ ./configure
pi@hbox:~ $ make
pi@hbox:~ $ sudo make install
pi@hbox:~ $ sudo mkdir -p /usr/local/etc/opendv
pi@hbox:~ $ sudo mkdir -p /usr/local/var/log/opendv

Configure DStarRepeater

Execute dstarrepeaterconfig on the target as follows.

Replace KF5SVQ with your call sign.