Novel Fibonacci and non-Fibonacci structure in
the sunflower: results of a citizen science
experiment - The Royal Society Publishing
Wednesday, February 24, 2021
Wednesday, February 17, 2021
Computer pioneer, Bill Joy, created the Vi text editor. Vi has made its way onto nearly every UNIX and Linux computer and is used by kernel developers, system administrators, programmers, and users. The learning curve is steep; however, its efficiency pays off over time. One hour per day for five to six years digging through kernel source code with ctags will allow you to become proficient with the editor. If you are already a C programmer and can work from the terminal quickly, then picking up Vi should be easy for you. My notes below describe how to setup VIM, a fork of Vi that includes features such as color syntax highlighting.
nmap <silent> <c-n> :NERDTreeToggle<CR>
nnoremap <silent> <c-m> :TlistToggle<CR>Vim should be good to go at this point. cd back into your source code directory and begin work. Finally, man vim will tell you more about how to use the editor.
Thursday, February 1, 2018
Hybrid boards with ARM processors integrate FPGAs with multicore ARM
processors over high speed buses. The ARM processor is termed the hard
processor system or HPS. Writing to the FPGA from the ARM processor is
typically performed via C from an embedded Linux build (yocto or
buildroot) running on the ARM core. A simple bitstream can also be
loaded into the FPGA fabric without using any ARM design blocks or
functionality in the ARM core.
|ModelSim Wave Output for the xor design|
Monday, August 15, 2016
The following requirements were in place for this project.
- Use course-grained locking strategy. Only lock data.
- Minimize critical sections.
- Fork five processes, all of which are attached to the controlling terminal.
- Create three threads in one of the five processes.
- Two of the threads will simulate packet processing.
- One of the threads will generate packets in a buffer.
- Properly utilize synchronization primitives and mutex locks.
- Maximize concurrency.
- Minimize latency.
- Ensure order of context switching is always random upon execution - i.e. don't control the scheduler.
- Utilize ARM DS-5 for building and debugging the application on the attached de0-Nano-SoC FPGA.
- Use autotools for building a shared library and link against the library with a driver program in DS-5.
- Compile the shared library and driver program using the Linaro GCC ARM-Linux-GNUEABI Hard Float toolchain version 4.8 that is included in the Altera DS-5 download.
- Compile the shared library and test program using the Linaro GCC ARM-Linux-GNUEABI Hard Float toolchain version 5.3 (latest stable from Linaro as of 08/15/16).
- Debug the multiprocess, multithreaded application using both toolchains from DS-5.
- Ensure that all possible errors from calls to pthread functions and other libc functions are properly handled.
|DS-5 disassembly / memory analysis - debugging multithreaded, multiprocess applications on ARM Powered boards|
|DS-5 Debug Configurations - Files|
|DS-5 Toolchain Editor|
Saturday, July 30, 2016
On a preemptive, timed sliced UNIX or Linux operating system (Solaris, AIX, Linux, BSD, OS X), sequences of program code from different software applications are executed over time on a single processor. A UNIX process is a schedulable entity. On a UNIX system, program code from one process executes on the processor for a time quantum, after which, program code from another process executes for a time quantum. The first process relinquishes the processor either voluntarily or involuntarily so that another process can execute its program code. This is known as context switching. When a process context switch occurs, the state of a process is saved to its process control block and another process resumes execution on the processor. Finally, A UNIX process is heavyweight because it has its own virtual memory space, file descriptors, register state, scheduling information, memory management information, etc. When a process context switch occurs, this information has to be saved, and this is a computationally expensive operation.
Concurrency refers to the interleaved execution of schedulable entities on a single processor. Context switching facilitates interleaved execution. The execution time quantum is so small that the interleaved execution of independent, schedulable entities, often performing unrelated tasks, gives the appearance that multiple software applications are running in parallel.
Concurrency applies to both threads and processes. A thread is also a schedulable entitity and is defined as an independent sequence of execution within a UNIX process. UNIX processes often have multiple threads of execution that share the memory space of the process. When multiple threads of execution are running inside of a process, they are typically performing related tasks.
While threads are typically lighter weight than processes, there have been different implementations of both across UNIX and Linux operating systems over the years. The three models that typically define the implementations across preemptive, time sliced, multi user UNIX and Linux operating systems are defined as follows: 1:1, 1:N, and M:N where 1:1 refers to the mapping of one user space thread to one kernel thread, 1:N refers to the mapping of multiple user space threads to a single kernel thread, and M:N refers to the mapping of N user space threads to M kernel threads.
In summary, both threads and processes are scheduled for execution on a single processor. Thread context switching is lighter in weight than process context switching. Both threads and processes are schedulable entities and concurrency is defined as the interleaved execution over time of schedulable entities on a single processor.
The Linux user space APIs for process and thread management are abstracted from alot of the details but you can set the level of concurrency and directly influence the time quantum so that system throughput is affected by shorter and longer durations of schedulable entity execution time.
Conversely, parallelism refers to the simultaneous execution of multiple schedulable entities over a time quanta. Both processes and threads can execute in parallel across multiple cores or multiple processors. On a multiuser system with preemptive time slicing and multiple processor cores, both concurrency and parallelism are often at play. Affinity scheduling refers to the scheduling of both processes and threads across multiple cores so that their concurrent and often parallel execution is close to optimal.
Software applications are often designed to solve computationally complex problems. If the algorithm to solve a computationally complex problem can be parallelized, then multiple threads or processes can all run at the same time across multiple cores. Each process or thread executes by itself and does not contend for resources with other threads or processes that are working on the other parts of the problem to be solved. When each thread or process reaches the point where it can no longer contribute any more work to the solution of the problem, it waits at the barrier. When all threads or processes reach the barrier, the output of their work is synchronized, and often aggregated by the master process. Complex test frameworks often implement the barrier synchronization problem when certain types of tests can be run in parallel.
Most individual software applications running on preemptive, time sliced, multiuser Linux and UNIX operating systems are not designed with heavy, parallel thread or parallel, multi-process execution in mind. Expensive, parallel algorithms often require multiple, dedicated processor cores with hard real time scheduling constrains. The following paper describes the solution to a popular, parallel algorithm; flight scheduling.
Last, when designing multithreaded and multiprocess software programs, minimizing lock granularity greatly increases concurrency, throughput, and execution efficiency. Multithreaded and multiprocess programs that do not utilize course-grained synchronization strategies do not run efficiently and often require countless hours of debugging. The use of semaphores, mutex locks, and other synchronization primitives should be minimized to the maximum extent possible in computer programs that share resources between multiple threads or processes. Proper program design allows for schedulable entities to run in parallel or concurrently with high throughput and minimum resource contention, and this is optimal for solving computationally complex problems on preemptive, time scliced, multi user operating systems without requiring hard real time scheduling.
After a fairly considerable amount of research in the above areas, I utilized the above design techniques for several successful, multi threaded and multi process software programs.
Thursday, June 30, 2016
|DE1-SoC GPIO Pins connected to lower power test diodes and Oscilloscope|
The following VHDL processes pulse the GPIO pins at different frequencies on the Altera DE1-SoC using multiple Phase-Locked Loops. Several diodes are connected to the GPIO banks and pulsed at a 50% duty cycle with 16mA across 3.3V. Each GPIO bank on the DE1-SoC has 36 pins. Pin 1 is pulsed at 20hz from GPIO bank 0, and pins 0 and 1 are pulsed at 30hz from GPIO bank 1. A direct mode PLL with locked output was configured using the Altera Quartus Prime MegaWizard. The PLL reference clock frequency is set to 50mhz, the output clock frequency is set to 50mhz, and the duty cycle is set to 50%. The pin mappings for GPIO banks 0 and 1 are documented on the DE1-SoC datasheet.
|Pulsed GPIO pins with low-power diodes attached via breadboard on DE1-SoC FPGA|
|DE1-SoC GPIO Bank 0 Pin 1|
Thursday, June 2, 2016
The DE1-SoC FPGA Development board from Terasic is powered by an integrated Altera Cyclone V FPGA and ARM MPCore Cortex-A9 processor. The FPGA and ARM core are connected by a high-speed interconnect fabric so you can boot Linux on the ARM core and then talk to the FPGA.The below configuration was built from the Terasic Design Reference sources.
A low-level hardware abstraction layer was programmed in C to configure the on-board audio codec chip. The NIOS II chip is stored in on-chip memory and a PLL driven, clock signal is fed into the audio chip. The Verilog code for the hardware design was generated from Qsys. The design supports configurable sample rates, mic in, and line in/out.
The DC934A features an LTC2607 16-Bit Dual DAC with i2c interface and an LTC2422 2-Channel 20-Bit uPower No Latency Delta Sigma ADC.
3.5mm audio cables are connected to the mic in and line out ports, respectively. The DE1-SoC is connected to an external display over VGA so that a local console can be managed via a connected keyboard and mouse when Linux is booted from uSD.
With GPIO pins accessible via the GPIO 0 and 1 breakouts, external LEDs can be pulsed directly from the Hard Processor System (HPS), FPGA, or the FPGA via the HPS.