The following requirements were in place for this project.
- Use course-grained locking strategy. Only lock data.
- Minimize critical sections.
- Fork five processes, all of which are attached to the controlling terminal.
- Create three threads in one of the five processes.
- Two of the threads will simulate packet processing.
- One of the threads will generate packets in a buffer.
- Properly utilize synchronization primitives and mutex locks.
- Maximize concurrency.
- Minimize latency.
- Ensure order of context switching is always random upon execution - i.e. don't control the scheduler.
- Utilize ARM DS-5 for building and debugging the application on the attached de0-Nano-SoC FPGA.
- Use autotools for building a shared library and link against the library with a driver program in DS-5.
- Compile the shared library and driver program using the Linaro GCC ARM-Linux-GNUEABI Hard Float toolchain version 4.8 that is included in the Altera DS-5 download.
- Compile the shared library and test program using the Linaro GCC ARM-Linux-GNUEABI Hard Float toolchain version 5.3 (latest stable from Linaro as of 08/15/16).
- Debug the multiprocess, multithreaded application using both toolchains from DS-5.
- Ensure that all possible errors from calls to pthread functions and other libc functions are properly handled.
|DS-5 disassembly / memory analysis - debugging multithreaded, multiprocess applications on ARM Powered boards|
|DS-5 Debug Configurations - Files|
|DS-5 Toolchain Editor|